1. Field of the Invention
The present invention relates to structures of semiconductor devices and fabricating methods of the same. More particularly, the present invention relates to structures of shallow trench isolation (STI) and dynamic random access memory (DRAM), and fabricating methods of the same.
2. Description of the Related Art
With progressively increased functions of current computer, the memory capacity required in any kind of computer is correspondingly getting larger and larger, and DRAM cells therefore need to be miniaturized continuously for further higher integration. In a deep sub-micron semiconductor process or a more advanced process, the lateral area for forming a DRAM cell and the accompanying storage capacitor is very small, and more sophisticated techniques are required to maintain the surface area of the storage capacitor for its storage capability.
Generally, the storage capacitors formed in DRAM can be divided into two categories according to their structures, namely, stacked capacitor and deep-trench capacitor. No matter which kind of capacitor structure is adopted, DRAM fabrication process gets more and more difficult as device dimensions are being decreased progressively.
On the other hand, in a fabrication process of a semiconductor device such as DRAM, an active area (AA) is usually defined and electrically isolated by forming a shallow trench isolation (STI) structure. When device dimensions are being decreased progressively, enhancing the isolation capability of STI structures is also an important issue.
There have been a variety of methods provided in the prior art for enhancing the isolation capability of STI structures. For example, U.S. Publication No. 2002-0179997 discloses a method that forms a doped region, just after the shallow trench is formed, under the bottom of an STI layer to serve as a channel stop layer, thereby preventing a leakage current between two adjacent active areas.
However, when the doped region is formed under the bottom of an STI layer for enhancing the isolation capability of the STI layer, other leakage problems occur. For example, it is inevitable that some P-type ions are implanted into the sidewall of the shallow trench in the channel stop implantation process to form another doped region therein, since a back-scattering effect may let some ions be implanted into the sidewall of the shallow trench. The doped region in the sidewall of the shallow trench will overlap with the source/drain formed later, so that the junction gradient at the boundary of the source/drain is increased to cause a larger electric field, which further induces a junction leakage.
FIG. 1 illustrates a cross-sectional view of a conventional DRAM cell, which includes a trench capacitor 101 disposed in a substrate 100, an STI layer 122, an active device 136, a buried strap 110 coupling the active device 136 to the trench capacitor 101, an N-doped layer 126 and a P-doped layer 130. The trench capacitor 101 includes a lower electrode 102, an inter-electrode dielectric layer 104, an upper electrode 106 and a collar oxide layer 108 surrounding the upper portion of the upper electrode 106.
The N-doped layer 126 is formed to electrically connect the lower electrodes 102 of all trench capacitors 101 in the memory array (not shown). The P-doped layer 130 is formed in the substrate 100 at a depth just under the bottom of the STI layer 122, also traversing the channel region of a vertical parasitic transistor that consists of the buried strap 110, the lower electrode 102, the collar oxide layer 108 and the upper electrode 106. Therefore, the insulating capability of the STI layer 122 is improved, and the threshold voltage of the parasitic transistor is raised. If the threshold voltage of the parasitic transistor were not raised in this manner, the channel thereof would be turned on easily to cause a leakage of the charges on the capacitor and therefore lower the storage capability. The P-doped layer 130 is usually formed with a P-type ion implantation process after the STI layer 122 is formed.
Moreover, since the P-doped region 130 must be formed at a depth just under the bottom of the STI layer 122 to effectively enhance the isolation capability, the P-doped layer 130 is formed close to the buried strap 110. Therefore, similar to the case mentioned above, the P-N junction gradient at the boundary of the buried strap 110 is increased, and a junction leakage is easily caused thereat.